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integrated device technology, inc. military and commercial temperature ranges december 1996 1996 integrated device technology, inc. dsc-2677/7 5.09 1 features: first-in/first-out dual-port memory bit organization IDT72021?k x 9 idt72031?k x 9 idt72041?k x 9 ultra high speed IDT72021?5ns access time idt72031?5ns access time idt72041?5ns access time easily expandable in word depth and/or width asynchronous and simultaneous read and write functionally equivalent to idt7202/03/04 with output enable ( oe ) and almost empty/almost full flag ( aef ) ? four status flags: full, empty, half-full (single device mode), and almost empty/almost full (7/8 empty or 7/8 full in single device mode) ? output enable controls the data output port ? auto-retransmit capability ? available in 32-pin dip and plcc ? military product compliant to mil-std-883, class b ? industrial temperature range (-40 o c to +85 o c) is avail able, tested to military electrical specifications description: IDT72021/031/041s are high-speed, low-power, dual-port memory devices commonly known as fifos (first-in/first- out). data can be written into and read from the memory at independent rates. the order of information stored and ex- tracted does not change, but the rate of data entering the fifo might be different than the rate leaving the fifo. unlike a static ram, no address information is required because the read and write pointers advance sequentially. the IDT72021/ 031/041s can perform asynchronous and simultaneous read and write operations. there are four status flags, ( hf , ff , ef , aef ) to monitor data overflow and underflow. output enable ( oe ) is provided to control the flow of data through the output port. additional key features are write ( w ), read ( r ), retrans- mit ( rt ), first load ( fl ), expansion in ( xi ) and expansion out ( xo ). the IDT72021/031/041s are designed for those appli- cations requiring data control flags and output enable ( oe ) in multiprocessing and rate buffer applications. the IDT72021/031/041s are fabricated using idts cmos technology. military grade product is manufactured in compli- ance with the latest version of mil-std-883, class b, for high reliability systems. IDT72021 idt72031 idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 w r xi 2677 drw 01 write control write pointer read pointer reset logic read control flag logic expansion logic data input (d 0 Cd 8 ) ram array 1024 x 9 2048 x 9 4096 x 9 1 2 data outputs (q 0 Cq 8 ) three- state buffers 1024/ 2048/ 4096 aef ef ff fl/rt xo/hf rs oe the idt logo is a registered trademark of integrated device technology, inc. fast is a trademark of national semiconductor co. functional block diagram for latest information contact idt's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.09 2 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 pin configurations pin descriptions symbol name i/o description d 0 ? 8 inputs i data inputs for 9-bit wide data. rs reset i when rs is set low, internal read and write pointers are set to the first location of the ram array. hf and ff go high, and aef and ef go low. a reset is required before an initial write after power-up. r and w must be high during rs cycle. w write i when write is low, data can be written into the ram array sequentially, independent of read. in order for write to be active, ff must be high. when the fifo is full ( ff -low), the internal write operation is blocked. r read i when read is low, data can be read from the ram array sequentially, independent of write. in order for read to be active, ef must be high. when the fifo is empty ( ef -low), the internal read operation is blocked. the three-state output buffer is controlled by the read signal and the external output control (oe ). fl / rt first load/ i this is a dual-purpose input. in the single device configuration ( xi grounded), activating retransmit ( fl / rt -low) will set the internal read pointer to the first location. there is no effect on the write pointer. r and w must be high before setting fl / rt low. retransmit is not compatible with depth expansion. in the depth expansion configuration, fl / rt -low indicates the first activated device. xi expansion in i in the single device configuration, xi is grounded. in depth expansion or daisy chain expansion, xi is connected to xo (expansion out) of the previous device. oe output enable i when oe is set high, the data flow through the three-state output buffer is inhibited regardless of an active read operation. a read operation does increment the read pointer in this situation. when oe is set low, q 0 -q 8 are still in a high impedance condition if no read occurs. for a complete read operation with data appearing on q 0 -q 8 , both r and oe should be asserted low. ff full flag o when ff goes low, the device is full and further write operations are inhibited. when ff is high, the device is not full. ef empty flag o when ef goes low, the device is empty and further read operations are inhibited. when ef is high, the device is not empty. aef almost-empty/ o when aef is low, the device is empty to 1/8 full or 7/8 to completely full. when aef is high, the device is greater than 1/8 full, but less than 7/8 full. xo / hf expansion out/ o this is a dual purpose output. in the single device configuration ( xi grounded), the device is more than half full when hf is low. in the depth expansion configuration ( xo connected to xi of the next device), a pulse is sent from xo to xi when the last location in the ram array is filled. q 0 Cq 8 outputs o data outputs for 9-bit wide data. retransmit almost-full flag half-full flag 2677 tbl 01 plcc top view dip top view d 2 5 d 1 6 d 0 7 xi 8 aef 9 ff 10 q 0 11 q 1 12 q 2 13 d 6 d 7 fl / rt rs oe ef xo / hf q 7 q 6 29 28 27 26 25 24 23 22 21 4 3 2 1 32 31 30 14 15 16 17 18 19 20 q 3 q 8 gnd gnd r q 4 q 5 d 3 d 8 w v cc v cc d 4 d 5 index j32-1 2677 drw 03 v cc d 4 d 5 d 6 d 7 fl / rt rs oe xo / hf ef q 7 q 6 q 5 q 4 r gnd v cc w d 8 d 3 d 2 d 1 d 0 xi aef ff q 0 q 1 q 2 q 3 q 8 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 d32-1 2677 drw 02
5.09 3 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 recommended dc operating conditions symbol parameter min. typ. max. unit v ccm military supply 4.5 5.0 5.5 v voltage v ccc commercial 4.5 5.0 5.5 v supply voltage gnd supply voltage 0 0 0 v v ih input high voltage 2.0 v commercial v ih input high voltage 2.2 v military v il (1) input low voltage 0.8 v commercial and military note: 2677 tbl 05 1. 1.5v undershoots are allowed for 10ns once per cycle. status flag number of words in fifo 1k 2k 4k ff aef hf ef 00 0hlhl 1-127 1-255 1-511 h l h h 128-512 256-1024 512-2048 hhhh 513-896 1025-1792 2049-3584 h h l h 897-1023 1793-2047 3585-4095 h l l h 1024 2048 4096 l l l h capacitance (t a = +25 c, f = 1.0 mhz) symbol parameter (1) condition max. unit c in input capacitance v in = 0v 10 pf c out output capacitance v out = 0v 10 pf note: 2677 tbl 03 1. these parameters are sampled and not 100% tested. 2677 tbl l 02 absolute maximum ratings (1) symbol rating com?. mil. unit v term terminal voltage C0.5 to +7.0 C0.5 to +7.0 v with respect to gnd t a operating 0 to +70 C55 to +125 c temperature t bias temperature C55 to +125 C65 to +135 c under bias t stg storage C55 to +125 C65 to +155 c temperature i out dc output 50 50 ma current note: 2677 tbl 04 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabilty.
5.09 4 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 dc electrical characteristics ?IDT72021 (commercial: v cc = 5.0v 10%, t a = 0 c to +70 c; military: v cc = 5v 10%, t a = C55 c to +125 c) IDT72021 IDT72021 IDT72021 IDT72021 commercial military commercial military t a =25,35ns t a =30,40ns t a =50ns t a =50ns symbol parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit i li (1) input leakage current C1 1 C10 10 C1 1 C10 10 m a (any input) i lo (2) output leakage current C10 10 C10 10 C10 10 C10 10 m a v oh output logic 1 voltage 2.4 2.4 2.4 2.4 v i oh = C2ma v ol output logic 0 voltage 0.4 0.4 0.4 0.4 v i ol = 8ma i cc1 (3,4) active power supply 120 140 50 80 70 100 ma current i cc2 (3) standby current 12 20 5 8 8 15 ma ( r = w = rs = fl / rt = v ih ) i cc3 (3) power down current 500 900 500 900 m a (all input = v cc C 0.2v) 2677 tbl 06 dc electrical characteristics ?idt72031, idt72041 (commercial: v cc = 5.0v 10%, t a = 0 c to +70 c; military: v cc = 5v 10%, t a = C55 c to +125 c) idt72031 idt72031 idt72041 idt72041 commercial military t a =35,50ns t a =40,50ns symbol parameter min. typ. max. min. typ. max. unit i li (1) input leakage current (any input) C1 1 C10 10 m a i lo (2) output leakage current C10 10 C10 10 m a v oh output logic 1 voltage i out = C2ma 2.4 2.4 v v ol output logic 0 voltage i out = 8ma 0.4 0.4 v i cc1 (3,5) active power supply current 75 120 100 150 ma i cc2 (3) standby current ( r = w = rs = fl / rt = v ih )8121225ma i cc3 (3) power down current (all input = v cc C 0.2v) 2 4 ma notes: 2677 tbl 07 1. measurements with 0.4 v in v cc . 2. r 3 v ih , 0.4 v out v cc . 3. i cc measurements are made with oe = high. 4. tested at f = 20mhz. 5. tested at f = 15.3 mhz.
5.09 5 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 ac electrical characteristics ?IDT72021 (1) (commercial: v cc = 5.0v 10%, t a = 0 c to +70 c; military: v cc = 5v 10%, t a = C55 c to +125 c) com? mil. com? mil. com? & mil. 72021l25 72021l30 72021l35 72021l40 72021l50 symbol parameter min. max. min. max. min. max. min. max. min. max. unit f s shift frequency 28.5 25 22.2 20 15 mhz t rc r cycle time 35 40 45 50 65 ns t a access time 25 30 35 40 50 ns t rr r recovery time 10 10 10 10 15 ns t rpw r pulse width (2) 25 30 35 40 50 ns t rlz r pulse low to data bus at low-z (3) 555 510ns t wlz w pulse high to data bus at low-z (3,4) 555 55ns t dv data valid from r pulse high 5 5 5 5 5 ns t rhz r pulse high to data bus at high-z (3) 18 20 20 25 30 ns t wc w cycle time 35 40 45 50 65 ns t wpw w pulse width (2) 25 30 35 40 50 ns t wr w recovery time 10 10 10 10 15 ns t ds data set-up time 15 18 18 20 30 ns t dh data hold time 0 0 0 0 5 ns t rsc rs cycle time 35 40 45 50 65 ns t rs rs pulse width (2) 25 30 35 40 50 ns t rss rs set-up time 25 30 35 40 50 ns t rsr rs recovery time 10 10 10 10 15 ns t rtc rt cycle time 35 40 45 50 65 ns t rt rt pulse width (2) 25 30 35 40 50 ns t rtr rt recovery time 10 10 10 10 15 ns t rsf1 rs to ef and aef low 35 40 45 50 65 ns t rsf2 rs to hf and ff high 35 40 45 50 65 ns t ref r low to ef low 25 30 30 35 45 ns t rff r high to ff high 25 30 30 35 45 ns t rpe r pulse width after ef high 25 30 35 40 50 ns t wef w high to ef high 25 30 30 35 45 ns t wff w low to ef low 25 30 30 35 45 ns t whf w low to hf low 35 40 45 50 65 ns t rhf r high to hf high 35 40 45 50 65 ns t wpf w pulse width after ff high 25 30 35 40 50 ns t rf r high to transitioning aef 35 40 45 50 65 ns t wf w low to transitioning aef 35 40 45 50 65 ns t oehz oe high to high-z (disable) (3) 0 12 0 15 0 17 0 20 0 25 ns t oelz oe low to low-z (enable) (3) 0 12 0 15 0 17 0 20 0 25 ns t aoe oe low data valid (q 0 Cq 8 ) 15 18 20 25 30 ns notes: 2677 tbl 08 1. timings referenced as in ac test conditions. 2. pulse widths less than minimum value are not allowed. 3. values guaranteed by design, not currently tested. 4. only applies to read data flow-through mode.
5.09 6 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 ac electrical characteristics ?idt72031, idt72041 (1) (commercial: v cc = 5.0v 10%, t a = 0 c to +70 c; military: v cc = 5v 10%, t a = C55 c to +125 c) com'l mil. com'l and mil. 72031l35 72031l40 72031l50 72041l35 72041l40 72041l50 symbol parameter min. max. min. max. min. max. unit f s shift frequency 22.2 20 15 mhz t rc r cycle time 45 50 65 ns t a access time 35 40 50 ns t rr r recovery time 10 10 15 ns t rpw r pulse width (2) 35 40 50 ns t rlz r pulse low to data bus at low-z (3) 5510ns t wlz w pulse high to data bus at low-z (3,4) 555ns t dv data valid from r pulse high 5 5 5 ns t rhz r pulse high to data bus at high-z (3) 20 25 30 ns t wc w cycle time 45 50 65 ns t wpw w pulse width (2) 35 40 50 ns t wr w recovery time 10 10 15 ns t ds data set-up time 18 20 30 ns t dh data hold time 0 0 5 ns t rsc rs cycle time 45 50 65 ns t rs rs pulse width (2) 35 40 50 ns t rss rs set-up time 35 40 50 ns t rsr rs recovery time 10 10 15 ns t rtc rt cycle time 45 50 65 ns t rt rt pulse width (2) 35 40 50 ns t rtr rt recovery time 10 10 15 ns t rsf1 rs to ef and aef low 45 50 65 ns t rsf2 rs to hf and ff high 45 50 65 ns t ref r low to ef low 30 35 45 ns t rff r high to ff high 30 35 45 ns t rpe r pulse width after ef high 35 40 50 ns t wef w high to ef high 30 35 45 ns t wff w low to ef low 30 35 45 ns t whf w low to hf low 45 50 65 ns t rhf r high to hf high 45 50 65 ns t wpf w pulse width after ff high 35 40 50 ns t rf r high to transitioning aef 45 50 65 ns t wf w low to transitioning aef 45 50 65 ns t oehz oe high to high-z (disable) (3) 017020025ns t oelz oe low to low-z (enable) (3) 017020025ns t aoe oe low data valid (q 0 Cq 8 ) 20 25 30 ns notes: 2677 tbl 09 1. timings referenced as in ac test conditions. 2. pulse widths less than minimum value are not allowed. 3. values guaranteed by design, not currently tested. 4. only applies to read data flow-through mode.
5.09 7 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 ac test conditions input pulse levels gnd to 3.0v input rise/fall times 5ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 1 2677 tbl 10 notes: 1. ef , ff , hf , and aef may change status during reset, but flags will be valid at t rsc . 2. w and r = v ih around the rising edge of rs . figure 2. reset figure 3. asynchronous write and read operation note: 1. assume oe is asserted low. t rsc t t rss t rss t rsf1 rs w r aef, ef hf, ff t rsr 2677 drw 05 t rsf2 rs t a r t rc data out valid data out valid t rpw t rlz t dv t a t rhz t rr t wc t wr t wpw data in valid data in valid t ds t dh q 0 Cq 8 d 0 Cd 8 2677 drw 06 w 2677 drw 04 30pf* 1.1k 5v to output pin 680 w or equivalent circuit figure 1. output load * includes scope and jig capacitances.
5.09 8 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 figure 4. full flag from last write to first read figure 5. empty flag from last read to first write figure 6. retransmit note: 1. assume oe is asserted low. last write r ignored write first read additional reads first write w ff t wff t rff 2677 drw 07 last read w ignored read first write additional writes first read ef r t ref t wef 2677 drw 08 valid valid t a data out (1) t rtc t rt rt w , r aef , hf , ef , ff t rtr flag valid 2677 drw 09
5.09 9 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 figure 7. empty flag timing figure 9. almost-empty/almost-full flag and half-full timings figure 8. full flag timing ef w r t wef t rpe 2677 drw 10 ff r w t rff t wpf 2677 drw 11 figure 10. output enable and read operation timings figure 9. almost-empty/almost-full flag and half-full timings w t rhf (7/8 full) almostCempty (1/8 fullC1) halfCfull (1/2) t whf t wf halfCfull + 1 almostCfull (7/8 full + 1) halfCfull (1/2) (7/8 full) almostCempty (1/8 fullC1) (1/8 full) t rf r hf aef 2677 drw 12 aef q0-8 oe data 1 second read by controlling oe terminate read cycle high impedance r data 1 t rc t rr t dv t oehz t oelz t aoe t a t rlz 2677 drw 13
5.09 10 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 r w xo 2677 drw 14 write to last physical location t xol t xoh read from last physical location t xol t xoh figure 11. expansion out w xi r 2677 drw 15 write to first physical location read from first physical location t xis t xir t xi t xis figure 12. expansion in operating configurations single device configuration the IDT72021/031/041 is in the single device configuration when the expansion in ( xi ) control input is grounded (see figure 13). write (w) data in (d) full flag (ff) reset (rs) 9 read (r) 9 data out (q) empty flag (ef) retransmit (rt) output enable (oe) expansion in (xi) hf aef 2677 drw 16 idt 72021/031/041 (halfCfull flag) figure 13. block diagram of single 1k/2k/4k x 9 fifo
5.09 11 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 width expansion configuration word width may be increased simply by connecting the corresponding input control signals of multiple devices. sta- tus flags ( ef , ff , hf , and aef ) can be detected from any one figure 14. block diagram of 1k/2k/4k x 18 fifo memory used in width expansion configuration data in (d) idt 72021/031/041 idt 72021/031/041 write (w) full flag (ff) reset (rs) output enable (oe) read (r) empty flag (ef) retransmit (rt) data out (q) xi xi 99 18 9 18 aef hf 2677 drw 17 aef hf 9 note: 1. flag detection is accomplished by monitoring the ff , ef , hf and aef signals on either (any) device used in the width expansion configuration. do not connect any output signals together. depth expansion (daisy chain) mode the IDT72021/031/041 can easily be adapted to applica- tions when the requirements are for greater than 1k/2k/4k words. figure 15 demonstrates depth expansion using three IDT72021/031/041s. any depth can be attained by adding additional devices. the IDT72021/031/041 operates in the depth expansion configuration when the following conditions are met: 1. the first device must be designed by grounding the first load ( fl ) control input. 2. all other devices must have fl in the high state. 3. the expansion out ( xo ) pin of each device must be tied to the expansion in ( xi ) pin of the next device. see figure 15. 4. external logic is needed to generate a composite full flag ( ff ) and empty flag ( ef ). this requires the oring of all ef s and oring of all ff s (i.e. all must be set to generate the correct composite ff or ef ). see figure 15. 5. the retransmit ( rt ) function and half-full flag ( hf ) are not available in the depth expansion mode. for addi- tional information refer to tech note 9: cascading fifos or fifo modules. compound expansion mode the two expansion techniques described above can be applied together in a straight forward manner to achieve large fifo arrays (see figure 16). bidirectional mode applications which require data buffering between two systems (each system capable of read and write operations) can be achieved by pairing IDT72021/031/041s as shown in figure 17. care must be taken to assure that the appropriate flag is monitored by each system (i.e., ff is monitored on the device where w is used; ef is monitored on the device where r is used). both depth expansion and width expansion may be used in this mode. data flow-through modes two types of flow-through modes are permitted: a read flow-through and write flow-through mode. for the read flow- through mode (figure 18), the fifo permits the reading of a single word after writing one word of data into an empty fifo. the data is enabled on the bus in (t wef + t a ) ns after the rising edge of w , called the first write edge. it remains on the bus until the r line is raised from low-to-high, after which the bus would go into a three-state mode after t rhz ns. the ef line would have a pulse showing temporary deassertion and then would be asserted. in the interval of time that r was low, more words can be written to the fifo (the subsequent writes after the first write edge will be deassert the empty flag); however, the same word (written on the first write edge), presented to the output bus as the read pointer, would not be incremented when r was low. on toggling r , the other words that are written to the fifo will appear on the output bus as in the read cycle timings. device. figure 14 demonstrates an 18-bit word width by using two IDT72021/031/041 devices. any word width can be at- tained by adding additional IDT72021/031/041s.
5.09 12 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 table i?eset and retransmit single device configuration/width expansion mode inputs internal status outputs mode rs rt xi read pointer write pointer ef ff hf aef reset 0 x 0 location zero location zero 0 1 1 0 retransmit 1 0 0 location zero unchanged x x x x read/write 1 1 0 increment (1) increment (1) xxxx note: 2677 tbl 11 1. pointer will increment if flag is high. table ii?eset and first load truth table depth expansion/compound expansion mode inputs internal status outputs mode rs fl xi read pointer write pointer ef ff reset first device 0 0 (1) location zero location zero 0 1 reset all other devices 0 1 (1) location zero location zero 0 1 read/write 1 x (1) x x x x note: 2677 tbl 12 1. xi is connected to xo of previous device. see figure 15. rs = reset input fl / rt = first load/retransmit, ef = empty flag output, ff = flag full output, xi = expansion input, hf = half-full flag output, aef = almost empty/almost full flag. in the write flow-through mode (figure 18), the fifo permits the writing of a single word of data immediately after reading one word of data from a full fifo. the r line causes the ff to be deasserted but the w line, being low causes it to be asserted again in anticipation of a new data word. on the rising edge of w , the new word is loaded in the fifo. the w line must be toggled when ff is not asserted to write new data in the fifo and to increment the write pointer. for additional information refer to tech note 8: operating fifos on full and empty boundary conditions and tech note 6: designing with fifos. idt 72021/ 031/041 d w idt 72021/ 031/041 idt 72021/ 031/041 ff ff ff ef fl fl ef ef fl xo xi xo xi rs full empty v cc r 2677 drw 18 9 9 99 xi xo 9 q truth tables figure 15. block diagram of 3k/6k/12k x 9 fifo memory (depth expansion) note: 1. idt only guarantees depth expansion with identical idt part numbers and speed.
5.09 13 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 figure 16. compound fifo expansion note: 1. assume oe is asserted low. IDT72021/ 031/041 depth expansion block IDT72021/ 031/041 depth expansion block IDT72021/ 031/041 depth expansion block r, w, rs ??? ??? ??? 2677 drw 19 q 0 Cq n d 0 Cd n notes: 1. for depth expansion block see section od depth expansion and figure 15. 2. for flag detection see section on width expansion and figure 14. figure 18. read data flow-through mode 2677 drw 21 data out valid t rpe t ref t wef t wlz t a ef r w data in data out (1) figure 17. bidirectional fifo mode idt 7201a r b ef b hf b w a ff a w b ff b system a system b q b 0-8 d b 0-8 q a 0-8 2677 drw 20 r a hf a ef a idt 72021/ 031/041 d a 0-8 aef idt 72021/ 031/041 aef
5.09 14 military and commercial temperature ranges IDT72021, idt72031, idt72041 cmos asynchronous fifo with retransmit 1k x 9, 2k x 9, 4k x 9 figure 19. write data flow-through mode ordering information note: 1. assume oe is asserted low. 2677 drw 22 t a r data out valid data in valid t ds t dh t wff t wpf t rff data in w ff data out (1) idt xxxxx device type x speed x power x package x process/ temperature range blank b d j l 72021 72031 72041 25 30 35 40 50 2677 drw 23 commercial (0 c to+70 c) military (C55 c to+125 c) compliant to mil-std-883, class b cerdip plastic leaded chip carrier 72021Ccoml. only 72021Cmil. only 72021/031/041Ccoml. only 72021/031/041Cmil. only 72021/031/041Ccom'l & mil. low power 1024 x 9-bit fifo 2048 x 9-bit fifo 4096 x 9-bit fifo access time (ta) speed in nanoseconds

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